1. Field of the Invention
This invention relates to integrated circuit (IC) manufacture technologies, and more particularly, to a new IC package architecture with a variable dispensed compound and a method of manufacturing the same. With this IC package architecture, the dispensed compound can be formed from a suitably selected material by the manufacturer in accordance with actual application requirements.
2. Description of Related Art
Integrated circuits are widely used in computers and intelligent electronic devices. Since IC chips are very small in size, they are usually supplied in packages for easy handling and utilization. The manufacture of ICs involves very complicated processes which can involve several hundreds of steps and needs several months to complete. The semiconductor industry is composed of four major branches: IC design, wafer fabrication, wafer testing, and packaging, each being a highly specialized field which requires state-of-the-art technologies and large amounts of capitals to accomplish.
The manufacture of an IC package includes three essential steps: preparing a wafer, forming a predesigned circuit on the wafer, and finally packing each die (chip) cutting apart from the wafer in a package. The packaging process is the final stage in the IC manufacture.
Conventional packaging methods, however, only involve one single molding process to form a molded compound for enclosing the chip therein. In some IC products where the enclosed chips should be transparent to the outside, such as EPROM (erasable programmable read-only memory) and EEPROM (electrically erasable programmable read-only memory), the molding is performed by using relatively expensive materials, such as ceramic, to form the compound. The manufacturing cost is therefore very high. Moreover, the conventional packaging methods will not allow the compound to be variably formed with a selected color for identification purpose of the integrated circuit.
FIGS. 1A-1C are schematic sectional diagrams used to depict the architecture of a conventional IC package and the steps involved in the method for manufacturing this IC package.
Referring first to FIG. 1A, the IC package is to be constructed on a leadframe 10 which is formed with two major parts: a die pad 16 in the center and a number of package pins 22 on the periphery of the die pad 16. In the packaging process, the first step is to perform a die-attach process so as to mount a chip 20 (which is a die cut apart from a fabricated wafer) on the front side of the die pad 16.
Referring next to FIG. 1B, in the subsequent step, a wire-bonding process is performed so as to connect the bonding pads (not shown) on the chip 20 respectively via a plurality of wires 24 to the corresponding ones of the package pins 22.
Referring further to FIG. 1C, in the subsequent step, a molding process is performed so as to form a molded compound 26 which hermetically encloses the chip 20, the die pad 16, and the wires 24 therein, with only the outer end of the package pins 22 being exposed to the outside.
In the case of the foregoing IC package being used to enclose an ordinary chip other than EPROM or EEPROM, the molded compound 26 can be formed from a lowcost material, such as plastics. However, in the case of the foregoing IC package being used to enclose an EPROM chip or an EEPROM chip therein, the molded compound 26 should be formed with a transparent window that can allow ultraviolet light to pass therethrough during a reprogramming process to erase old data from the chip and program new data into the same. To provide the transparent window, a special (and relatively costly) material, such as ceramics, is used to form the molded compound 26. The high manufacturing cost of these IC packages make them considerably more expensive on the market.